1. Field of the Invention
The present invention relates to redundancy repair in a semiconductor memory such as a programmable read-only memory (PROM), more particularly to block-wise redundancy repair.
2. Description of the Related Art
Each memory cell (hereinafter, cell) in a PROM typically consists of a single transistor with a floating gate. The memory cell is programmed by injecting charge into or removing charge from the floating gate, thereby altering the threshold value of the transistor. It is known art to provide a PROM with redundant memory cells that can be used to replace defective memory cells, thereby raising the yield of the PROM manufacturing process by enabling defective PROMs to be repaired. In one known redundancy repair scheme, an entire block of memory cells, including the defective memory cell, is replaced with a redundant block of memory cells. One advantage of this scheme is that it reduces the size of the circuitry that generates address signals to select the redundant memory cells.
FIG. 8 shows the general structure of a conventional PROM of this type, having a normal cell array 1 and a redundant cell array 2A. FIG. 9 shows the circuit structure of these cell arrays. The circuit structures of the cell drain selection circuit 3, column decoder circuit 4, defective cell block column redundancy selection circuit 5, and row decoder circuit 8 in FIG. 8 are shown in FIGS. 3, 4, 5, and 7, respectively.
The normal cell array 1 in FIG. 9 is divided into a plurality of blocks. Cell block 10, for example, includes a pair of bit lines BL2, BL3 and the memory cells ML2, MR2, ML3, MR3, etc. connected thereto. The redundant cell array 2A has a single redundant cell block 20 with a similar structure, including a pair of redundant bit lines RBL0, RBL1 and a plurality of redundant cells RML0, RMR0, RML1, RMR1, etc. The columns of cells in the normal cell array 1 are selected by four address signals AY0, AY1, AY2, AY3, of which AY2 and AY3 distinguish between different cell blocks.
In redundancy repair, if the circled cell ML2 in FIG. 9 is defective, for example, the entire cell block 10 including the defective cell is replaced with the redundant cell block 20 in the following procedure.
From FIGS. 4 and 9, it can be seen that cell block 10 is selected when column address signal AY2 is high and column address signal AY3 is low. In the defective cell block column redundancy selection circuit 5 in FIG. 5, fuse F50 in fuse-programmable circuit 50 is cut, setting a redundancy enable signal FMAIN to the high logic level. A similar fuse is cut in fuse-programmable circuit 51, setting a fuse-programmable address signal FY2 to the high logic level, while the fuse in fuse-programmable circuit 52 is left uncut, setting a fuse-programmable address signal FY3 to the low logic level. As a result, when column address signal AY2 is high and column address signal AY3 is low, the defective cell block column redundancy selection circuit 5 outputs a signal that selects redundant bit line RMBL0 or RMBL1, depending on the value of address signal AY1, and redundant data RDATA are read from the redundant cell block 20 and amplified by a redundant sense amplifier.
FIG. 10 shows an example of a type of defect that may occur. The source terminal of memory cell transistor ML2 is shorted to ground through a certain resistance, so that bit line BL2 is pulled down to the ground level. This problem affects all of the memory cells connected to bit line BL2.
Moreover, if memory cell transistor ML2 is programmed to the low-threshold state so that it turns on when word line select signal WL1 is active, adjacent memory cell MR1 is also affected. More specifically, if memory cell transistor MR1 is also programmed to the low threshold state, then when memory cell MR1 is read, the current iMC that should flow through transistor MR1 is diminished by the current iL leaking through memory cell ML2, so bit line BL1 receives only the difference current (iMR1=iMC−iL). The reduced current reduces the operating margin of the memory with respect to voltage and temperature variations, and if the defect at memory cell ML2 worsens over time, memory cell MR1 may become unreadable.
On the other side of cell block 10, if bit line BL3 or the source terminal of transistor MR3 leaks current to ground, similar problems will occur when memory cell ML4 is read.
Accordingly, when defective block 10 is replaced by redundant block 20, it would be convenient if adjacent half-block 11 or 12, comprising bit line BL1 or BL4 and its connected memory cells, could also be replaced, but a conventional memory designed for block-by-block redundancy repair does not permit the replacement of half-blocks, and in any case conventional block redundancy repair schemes do not contemplate the replacement of non-defective blocks or half-blocks.
Japanese Patent Application Publication No. H11-273392 (in particular FIGS. 1-3) discloses a PROM in which, when a bit line is defective, the memory cells connected to the bit line are programmed to the high-threshold state to prevent the defect from affecting other memory cells, and the memory cells thus programmed are replaced by redundant cells. This scheme, however, requires memory cells to be replaced on a bit-line basis rather than a block basis, making the circuit that controls the replacement and the circuit that reads data from the redundant memory cells more complex than when redundancy repair is performed block-wise. In particular, it is necessary to store the addresses of individual defective bit lines. The programming process also becomes more complex because it is necessary to program both the redundant memory cells and the memory cells they replace.